Low power scalable DCT design based on scalers sharing multiplier [video coding applications]

This paper proposes a low power DCT architecture based on scalers sharing a multiplier, which reduces the computation complexity of matrix-vector multiplication by sharing a small set of products. The presented architecture also provides an easy approach for making a trade off between image quality and power dissipation through scaling the multiplier's precision. Experimental results on a hardware FPGA platform shows that more than 35% power saving can be achieved by replacing the shift-adder multipliers with the scalers sharing multipliers in the baseline design.