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Low power scalable DCT design based on scalers sharing multiplier [video coding applications]

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3 Author(s)
Liu Feng ; Inst. of Microelectron., Xidian Univ., China ; Dai Guoding ; Zhuang Yiqi

This paper proposes a low power DCT architecture based on scalers sharing a multiplier, which reduces the computation complexity of matrix-vector multiplication by sharing a small set of products. The presented architecture also provides an easy approach for making a trade off between image quality and power dissipation through scaling the multiplier's precision. Experimental results on a hardware FPGA platform shows that more than 35% power saving can be achieved by replacing the shift-adder multipliers with the scalers sharing multipliers in the baseline design.

Published in:

Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on  (Volume:3 )

Date of Conference:

18-21 Oct. 2004