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A DSP-coprocessor architecture for image/video applications [coding/decoding]

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2 Author(s)
Minxue Liang ; Inst. of Microelectron., Chinese Acad. of Sci., Beijing, China ; Jie Chen

With the recent advances in video applications such as video teleconferencing, HDTV, etc., there is an increasing demand for a high-performance processor to implement JPEG, MPEG, and H.264 coding/decoding. A VLSI based DSP-coprocessor architecture is proposed in this article. The chip was implemented using SYNOPSYS tools and can yield a clock rate of about 300 MHz. JPEG decoding is tested on this novel DSP. The chip architecture and the test result are shown in detail in this article.

Published in:

Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on  (Volume:3 )

Date of Conference:

18-21 Oct. 2004