Cart (Loading....) | Create Account
Close category search window
 

A DSP-coprocessor architecture for image/video applications [coding/decoding]

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Minxue Liang ; Inst. of Microelectron., Chinese Acad. of Sci., Beijing, China ; Jie Chen

With the recent advances in video applications such as video teleconferencing, HDTV, etc., there is an increasing demand for a high-performance processor to implement JPEG, MPEG, and H.264 coding/decoding. A VLSI based DSP-coprocessor architecture is proposed in this article. The chip was implemented using SYNOPSYS tools and can yield a clock rate of about 300 MHz. JPEG decoding is tested on this novel DSP. The chip architecture and the test result are shown in detail in this article.

Published in:

Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on  (Volume:3 )

Date of Conference:

18-21 Oct. 2004

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.