Referenced Items are not available for this document.
The reverse read characteristics of SONOS type flash memory is researched and a novel array architecture with reverse read operation is proposed in this paper. A divided common-source-line NOR architecture is adopted to realize reverse read operation which enlarges the difference of the threshold voltage between the erased cell and the programmed cell and accelerates the read operation. Meanwhile, it also reduces the program disturbance, simplifies the source-line decoder, high voltage switch circuit and charge pump design.
Published in:
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
(Volume:1
)
Date of Conference: 18-21 Oct. 2004
- Page(s):
- 699 - 702 vol.1
- Print ISBN:
- 0-7803-8511-X
- INSPEC Accession Number:
- 8435740
- Digital Object Identifier :
- 10.1109/ICSICT.2004.1435099
- Product Type:
- Conference Publications
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
