A novel reverse read array architecture for embedded SONOS type flash memory

The reverse read characteristics of SONOS type flash memory is researched and a novel array architecture with reverse read operation is proposed in this paper. A divided common-source-line NOR architecture is adopted to realize reverse read operation which enlarges the difference of the threshold voltage between the erased cell and the programmed cell and accelerates the read operation. Meanwhile, it also reduces the program disturbance, simplifies the source-line decoder, high voltage switch circuit and charge pump design.