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Technology for three dimensional integrated system-on-a-chip

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2 Author(s)
Kurino, H. ; Dept. of Bioeng. & Robotics, Tohoku Univ., Sendai, Japan ; Koyanagi, M.

We have proposed a wafer stacking technology to integrate various kinds of devices into 3D SoC. In 3D SoC each circuit layer is stacked and electrically connected vertically using a huge number of vertical interconnection. Hence, we can dramatically increase the wiring connectivity, reduce the number of long wiring and integrate various kinds of devices with different fabrication process sequences into one chip. In this paper, we describe a 3D microprocessor test chip consisting of three circuit layers and demonstrate the basic operation of the 3D microprocessor.

Published in:

Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on  (Volume:1 )

Date of Conference:

18-21 Oct. 2004

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