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An advanced in-line process control methodology has been developed and proposed in this paper for the more and more aggressive challenging DRAM deep trench etching technique. Deep trench capacitor is the key element of DRAM (Mandelman et al., 2003) and the deep trench etching is still a major process challenge on every technology node. To have enough cell storage capacitor with smaller cell size, the aspect ratio of DT (deep trench) is becoming larger: it was higher than 80 in 0.1μm generation. For better polysilicon filling in the trench after the etching, sidewall angle need to be precisely controlled. In this paper, advanced modeling techniques and control algorithms are employed to control this challenging deep trench etch process. A real life example demonstrates the feasibility of the modeling and control methodologies.