Device physics and integrated device and circuit simulation of carrier field effect transistor with effective channel length of 5-30 nm and its integrated circuits in system-on-a-chip

We have developed complementary dual carrier field effect transistor (CDCFET) and CDCFET SOC in 1999. The two-dimensional structure of a DCFET is as shown. Eight papers were published in three international conferences to report the progress of our development work concerning CDCFET SOC. In this paper, we present the device physics and integrated device and circuit simulation of DCFET including low noise amplifier (LNA), power amplifier and switching circuits. Based on these theoretical studies, we have designed SOI Si DCFET circuits and DCFET devices with effective channel length of 5-30 nm as well as SiGe power amplifier DCFET. These designed SOI Si and SiGe DCFET have been fabricated using lithographic equipment for IC linewidth greater than 65nm.