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A parallel implementation of the message-passing decoder of LDPC codes using a reconfigurable optical model

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4 Author(s)
Babvey, S. ; Dept. of Comput. Sci., Georgia State Univ., Atlanta, GA, USA ; Bourgeois, A.G. ; Fernandez-Zepeda, J.A. ; McLaughlin, S.W.

In this paper we propose a constant-time algorithm for parallel implementation of the message-passing decoder of low density parity check (LDPC) codes on the linear array with a reconfigurable pipelined bus system (LARPBS), achieving the minimum number of processors required for a fully parallel implementation. Dynamic reconfiguration provides flexibility to code changes and efficient message routing. To decode a different code, we may simply set up the required connections between the bit-nodes and check-nodes by modifying the initialization phase of the LARPBS algorithm. No extra wiring or hardware changes are required, as compared to other existing approaches. Moreover, the same hardware can implement the decoder in both probability and logarithm domains. The LARPBS also allows reducing the number of the bus cycles required for processor communications to a small constant, regardless of the code length. We illustrate that the LARPBS is an efficient and fast model for implementing the decoder.

Published in:

Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing, 2005 and First ACIS International Workshop on Self-Assembling Wireless Networks. SNPD/SAWN 2005. Sixth International Conference on

Date of Conference:

23-25 May 2005