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Parallel FPGA implementation of self-organizing maps

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4 Author(s)
K. Ben Khalifa ; Inst. Superieur des Sci. Appliquees et de Technol., Sousse, Tunisia ; B. Girau ; F. Alexandre ; M. H. Bedoui

This paper presents an area-saving parallel implementation of a self-organizing map neural network (SOM) on FPGA. The purpose is to make available a finer grain of parallelism to be used in massively SIMD parallel SOM system architectures. We have handled a serial arithmetics (most significant bit first: MSBF and least significant bit first: LSBF), to process the different mathematical operations. Above all, our work has been oriented in such a way to get a light, easy to wear system for classification of vigilance states in humans from electroencephalographic (EEG) signals. The performances of our implementation in terms of area, speed and especially power consumption are highly satisfactory.

Published in:

Microelectronics, 2004. ICM 2004 Proceedings. The 16th International Conference on

Date of Conference:

6-8 Dec. 2004