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In this paper, a new technique for the dual-threshold voltage assignment with more efficiency is proposed. In the proposed method, an assignment priority factor which quantifies the reduction in the subthreshold current versus the delay increase is defined and utilized to select the proper gate(s). Using the factor, the gates with more decrease in the subthreshold leakage current and less delay penalty after the assignment are given a higher priority. This leads to more high threshold voltage gates and hence, a more static power reduction. The technique is applied to the ISCAS85 benchmarks achieving up to about 25% reduction in the subthreshold leakage compared to the conventional technique.
Date of Conference: 6-8 Dec. 2004