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This paper presents the outcome of a novel technique for mapping a class of high data width algorithms to low data width for efficient hardware implementation. The complexity of mapping an algorithm in hardware directly depends upon the data path size as all the registers and computational blocks depend on this size. Reducing the data path requirement can result in substantial savings in hardware. Folding techniques classically reduce the bit-widths. Our techique reduces the data path width without folding or timesharing the hardware resources. The technique is implemented on the advanced encryption standard (AES) algorithm and substantial savings in hardware cost is reported. Using this technique the 32-bit AES is implemented on a byte-systolic 8-bit architecture. The proposed crypto processor architecture resulted in efficient hardware resource utilization reducing data-path, buses, registers and memories to 8-bits, minimizing control logic, area and power. Unlike commercially available AES architectures, which incorporate separate hardware modules for key expansion, the proposed crypto processor design reuses the same architecture for both key expansion and encryption. The proposed design offers moderately high data rates when mapped on FPGA.