Cart (Loading....) | Create Account
Close category search window
 

Mapping of high-bit algorithm to low-bit for optimized hardware implementation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Farhan, S.M. ; Univ. of Eng. & Technol., Taxila, Pakistan ; Khan, S.A. ; Jamal, H.

This paper presents the outcome of a novel technique for mapping a class of high data width algorithms to low data width for efficient hardware implementation. The complexity of mapping an algorithm in hardware directly depends upon the data path size as all the registers and computational blocks depend on this size. Reducing the data path requirement can result in substantial savings in hardware. Folding techniques classically reduce the bit-widths. Our techique reduces the data path width without folding or timesharing the hardware resources. The technique is implemented on the advanced encryption standard (AES) algorithm and substantial savings in hardware cost is reported. Using this technique the 32-bit AES is implemented on a byte-systolic 8-bit architecture. The proposed crypto processor architecture resulted in efficient hardware resource utilization reducing data-path, buses, registers and memories to 8-bits, minimizing control logic, area and power. Unlike commercially available AES architectures, which incorporate separate hardware modules for key expansion, the proposed crypto processor design reuses the same architecture for both key expansion and encryption. The proposed design offers moderately high data rates when mapped on FPGA.

Published in:

Microelectronics, 2004. ICM 2004 Proceedings. The 16th International Conference on

Date of Conference:

6-8 Dec. 2004

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.