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This paper presents an on-chip interconnection infrastructure based on ARM's AHB standard to obtain a bus working beyond one gigahertz. All major design blocks necessary to implement reliable interconnect infrastructures for DSP platforms are presented. This interconnect infrastructure is implemented as a hard IP module to get the maximum performance out of TSMC's 0.18 μm CMOS technology. As a result, a bus operating at 1.4 GHz capable of transferring 2.8 giga data items per second was successfully designed.