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Architecture and implementation of a highly parallel single-chip video DSP

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4 Author(s)
H. Yamauchi ; NTT Public Corp., Kanagawa, Japan ; Y. Tashiro ; T. Minami ; Y. Suzuki

The architecture of a single-chip video DSP capable of attaining a maximum performance of 300-MOPS (mega operations per second) using 0.8-μm CMOS technology is described. The DSP is designed for the many applications regarding p×64 kb/s single-board video codecs based on DSPs that have roughly ten times the performance of conventional DSPs. Highly parallel architectures that allow four pipelined processing units to be integrated into one chip are studied extensively. The authors consider data path configurations, program sequencing control, and microinstructions that effectively support multiple pipeline processing. A prototype DSP is fabricated using 0.8-μm CMOS technology, and some performance evaluations are presented

Published in:

IEEE Transactions on Circuits and Systems for Video Technology  (Volume:2 ,  Issue: 2 )