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Voltage and sizing optimization for low power buffered digital designs

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5 Author(s)
F. Farbiz ; Dept. of ECE, Tehran Univ., Iran ; A. Behnam ; M. Emadi ; B. Esfandiarpoor
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A circuit design style with separate logic and buffer stages is investigated for its energy and delay characteristics. Then a new numerical approach is proposed for determining the optimum transistor sizing and supply voltage according to the minimum energy-delay product as a figure of merit (FOM). The results agree perfectly with the simulation data gathered from the SPICE simulation and are much more accurate than the ones proposed in the previous works.

Published in:

Microelectronics, 2004. ICM 2004 Proceedings. The 16th International Conference on

Date of Conference:

6-8 Dec. 2004