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A DSP architecture for motion estimation accelerating

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4 Author(s)
Zhang Chun ; Dept. of Electron. Eng., Tsinghua Univ., Beijing, China ; Yang Kun ; Mai Songping ; Wang Zhihua

Motion estimation (ME) consumes the majority of computation capacity of a DSP in video compression applications. A modified DSP architecture, to accelerate ME algorithms, is presented in this paper. The proposed SIMD and VLIW architecture is a trade-off between ASIC implementation and DSP implementation of ME, which can perform subtract, absolute and add (SAA) operations on 8 pixels and fetch 8 new pixels from memory at the same time. A flexible align addressing mode is provided to support efficient and continuous SAA operation on a video stream. The DSP is estimated to be 20 times faster than the SISD architecture in performing ME algorithms.

Published in:

Intelligent Multimedia, Video and Speech Processing, 2004. Proceedings of 2004 International Symposium on

Date of Conference:

20-22 Oct. 2004