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A cycle-efficient sample-parallel EBCOT architecture for JPEG2000 encoder

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5 Author(s)
Zhao Xing ; Inst. of VLSI Design, Zhejiang Univ., Hangzhou, China ; Yang Ye ; Qin Xing ; Wu Tuo
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In this paper, a novel cycle-efficient sample-parallel architecture for an EBCOT entropy encoder, used in JPEG2000, is proposed. The architecture consists of a pass-parallel context modeling unit capable of simultaneous processing of four samples, and a pipelined binary arithmetic coder running at double the system clock rate to match the processing rate of the context modeling unit. Simulation results show that this design reduces processing time by more than 50% to 60% compared with previous pass-parallel architectures, and is able is process a 512×512 grayscale image in approximately 0.005 second at 100 MHz system clock rate.

Published in:

Intelligent Multimedia, Video and Speech Processing, 2004. Proceedings of 2004 International Symposium on

Date of Conference:

20-22 Oct. 2004