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This paper proposes a new FRAM design style based on grounded-plate PMOS-gate (GPPG) cell architecture. A GPPG cell consists of a PMOS access transistor and a ferroelectric capacitor. Its plate is grounded. The proposed scheme employs three novel operating methods: 1) VDD precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore. Because this configuration doesn't need the on-pitch plate control circuitry, it is effective in realizing cost-effective chip sizes. Implementation for an experimental 2.5-V, 2-Mb FRAM prototype design in a 0.5-μm technology shows a cell array efficiency of 57 %, an access time of 85 ns and an active current of 12 mA, respectively.