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On the implementation of an efficient FPGA-based CFAR processor for target detection

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3 Author(s)
R. Cumplido ; Computer Science Department, INAOE, P.O. Box 51 & 216, Tonantzintla, Puebla, 72000, Mexico ; C. Torres ; S. Lopez

Real-time performance of adaptive digital signal processing algorithms is required in many applications but it often means a high computational load for many conventional processors. In this paper, we present a configurable hardware architecture for adaptive processing of noisy signals for target detection based on Constant False Alarm Rate (CFAR) algorithms. The architecture has been designed to deal with parallel/pipeline processing and to be configured for three version of CFAR algorithms, the Cell-Average, the Max and the Min CFAR. The proposed architecture has been implemented on a Field Programmable Gate Array (FPGA) device providing good performance improvements over software implementations. FPGA implementation results are presented and discussed.

Published in:

Electrical and Electronics Engineering, 2004. (ICEEE). 1st International Conference on

Date of Conference:

8-10 Sept. 2004