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Spatial versus temporal stability issues in image processing neuro chips

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3 Author(s)
Matsumoto, T. ; Dept. of Electr. Eng., Waseda Univ., Tokyo, Japan ; Kobayashi, H. ; Togawa, Y.

A typical image processing neuro chip consists of a regular array of very simple cell circuits. When it is implemented by a CMOS process, two stability issues naturally arise. First, parasitic capacitors of MOS transistors induce temporal dynamics. Since a processed image is given as the stable limit point of the temporal dynamics, a temporally unstable chip is unusable. Second, because of the array structure, the node voltage distribution induces spatial dynamics, and it could behave in a wild manner, e.g. oscillatory. The main contributions are: (i) a clarification of the spatial stability issue; (ii) explicit if and only if conditions for the temporal and the spatial stability in terms of circuit parameters; (iii) a rigorous explanation of the fact that even though the spatial stability is stronger than the temporal stability, the set of parameter values for which the two stability issues disagree is of (Lebesgue) measure zero; and (iv) theoretical estimates of the processing speed

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Neural Networks, IEEE Transactions on  (Volume:3 ,  Issue: 4 )