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Hierarchical systolic array design for full-search block matching motion estimation

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1 Author(s)
F. Gebali ; Dept. of Electr. & Comput. Eng., Victoria Univ., BC, Canada

We present here a hierarchical design methodology for the full-search block matching motion estimation. The methodology takes into account input data timing specifications and well as buffering requirements. System performance is manipulated by selecting some of the algorithm variables for pipelining or broadcasting. The design strategy also allows modifying time and hardware complexities at each level of the hierarchy in order to match system speed and hardware complexity to design specifications.

Published in:

Signal Processing and Information Technology, 2004. Proceedings of the Fourth IEEE International Symposium on

Date of Conference:

18-21 Dec. 2004