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Radiation hardened high performance CMOS VLSI circuit designs

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1 Author(s)
Hatano, H. ; Dept. of Electron., Shizuoka Inst. of Sci. & Technol., Japan

For space or nuclear plant applications, radiation tolerant high performance CMOS VLSI circuit designs, utilising scaled CMOS/SOS technology and scaled bulk CMOS technology, have been reviewed, placing strong emphasis on total dose radiation hardness. Based on radiation induced degradations for conventional CMOS circuits, such as inverters, ring oscillators and memory circuits, total dose radiation hardening technologies have been discussed. It is shown that low temperature process and thin oxide introductions are effective for radiation induced threshold voltage shift reduction. In addition to device/process technologies for total dose radiation hardening, usefulness for NAND logics and static circuits in radiation tolerant CMOS VLSI designs, are shown. Latchup immunity and SEU immunity have also been discussed, for both SOS and bulk devices. CMOS/SOS radiation hardened VLSIs and bulk CMOS radiation hardened VLSIs which have been developed by utilising above mentioned technologies, are reported

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Circuits, Devices and Systems, IEE Proceedings G  (Volume:139 ,  Issue: 3 )