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The effect of IrO2--IrO2--Hf--LaAlO3 gate dielectric on the bias-temperature instability of 3-D GOI CMOSFETs

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6 Author(s)
Yu, D.S. ; Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsinchu, Taiwan ; Liao, C.C. ; Cheng, C.F. ; Chin, A.
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We have studied the bias-temperature instability of three-dimensional self-aligned metal-gate/high-/spl kappa//Germanium-on-insulator (GOI) CMOSFETs, which were integrated on underlying 0.18 μm CMOSFETs. The devices used IrO2--IrO2-Hf dual gates and a high-/spl kappa/ LaAlO3 gate dielectric, and gave an equivalent-oxide thickness (EOT) of 1.4 nm. The metal-gate/high-/spl kappa//GOI p-and n-MOSFETs displayed threshold voltage (VT) shifts of 30 and 21 mV after 10 MV/cm, 85/spl deg/C stress for 1 h, comparable with values for the control two-dimensional (2-D) metal-gate/high-/spl kappa/-Si CMOSFETs. An extrapolated maximum voltage of -1.2 and 1.4 V for a ten-year lifetime was obtained from the bias-temperature stress measurements on the GOI CMOSFETs.

Published in:

Electron Device Letters, IEEE  (Volume:26 ,  Issue: 6 )