Optimizing program disturb fault tests using defect-based testing

Nonvolatile memories (NVMs) are susceptible to a special type of faults known as program disturb faults. These faults are described using logical fault models and often functional tests are used to detect different faults that occur under such models. The use of functional fault models and tests results in the simplification of the testing process, although such tests can be very long. In this paper, we present a defect-based model that can be used to model different disturb faults in NVM. The relationship between defect location and fault manifestation is first established using electrical simulation. Next, the use of stress tests and margin read schemes and how they are used to detect disturb faults is discussed. Using electrical simulation results, we show that defect-based testing can be used to optimize the cost of program disturb tests of NVM.