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A coarse-grain phased logic CPU

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3 Author(s)
Reese, R.B. ; Electr. & Comput. Eng. Dept., Mississippi State Univ., MS, USA ; Thornton, M.A. ; Traver, C.

This paper describes an asynchronous design tool flow known as phased logic that converts a clocked design into an asynchronous design implemented as a micropipeline using two-phase control and bundled data signaling. Example designs include variations of a double-precision floating-point clipping operation mapped to two commercial standard cell libraries (0.18μ and 0.13μ) and a five-stage pipelined MIPs-compatible integer unit mapped to the 0.13μ library. The design style includes a feature known as early evaluation, which is a generalized form of bypass that allows the self-timed design to recover some of the inherent latch delay penalty in micropipelines.

Published in:

Computers, IEEE Transactions on  (Volume:54 ,  Issue: 7 )

Date of Publication:

July 2005

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