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Isolation charge pump fabricated in silicon on sapphire CMOS technology

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3 Author(s)
Culurciello, E. ; Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA ; Pouliquen, P.O. ; Andreou, A.G.

The design, fabrication and testing of a four-stage charge-pump fabricated in a 0.5 μm silicon-on-sapphire CMOS technology is reported. The charge pump can generate a 2.68 V output with a 3.3 V input power supply, consuming 2.5 mA. The performance of the architecture is optimised by judiciously employing MOS transistors with different threshold (0, 0.3 and 0.7 V) in the different parts of the circuit. The charge pump input and output power supplies are galvanically isolated to over 800 V by means of the dielectric properties of the coupling capacitors and the insulating sapphire substrate.

Published in:

Electronics Letters  (Volume:41 ,  Issue: 10 )