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Low-power parallel multiplier with column bypassing

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3 Author(s)
M. -C. Wen ; Dept. of Comput. Sci., Nat. Chung-Hsing Univ., Taichung, Taiwan ; S. -J. Wang ; Y. -N. Lin

A low-power parallel multiplier design, in which some columns in the multiplier array can be turned-off whenever their outputs are known, is proposed. This design maintains the original array structure without introducing extra boundary cells, as was the case in previous designs. Experimental results show that it saves 10% of power for random input. Higher power reduction can be achieved if the operands contain more 0's than 1's.

Published in:

Electronics Letters  (Volume:41 ,  Issue: 10 )