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Formal verification of VHDL descriptions in the Prevail environment

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3 Author(s)
Borrione, D.D. ; Joseph Fourier Univ., Grenoble, France ; Pierre, L.V. ; Salem, A.M.

Prevail, a formal verification environment for proving the equivalence of two very-high-speed integrated circuit hardware description language (VHDL) design architectures, is described. For simple bit-level combinational descriptions, the environment calls upon a tautology checker. For parameterized repetitive structures and for more abstract sequential designs, the program translates descriptions into recursive functions according to predefined templates and generates a theorem acceptable to the Bover-Moore theorem prover. The specification, implementation, and functional representation of a sequential example are presented.<>

Published in:

Design & Test of Computers, IEEE  (Volume:9 ,  Issue: 2 )