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A VHDL fault diagnosis tool using functional fault models

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3 Author(s)
Pitchumani, V. ; Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA ; Mayor, P. ; Radia, N.

The development and implementation of an algorithm that forms the basis of a very-high-speed integrated circuit hardware description language (VHDL) fault diagnosis tool (VFDT) are discussed. Given a VHDL description, a compiler creates an internal representation suitable for simulation and fault diagnosis. VFDT diagnoses faults in this representation hierarchically using the stuck-at fault model at the first level and the arbitrary-failure model at the second level. It reasons from first principles by means of constraint suspension. Examples of fault diagnosis using the VFDT are described.<>

Published in:

Design & Test of Computers, IEEE  (Volume:9 ,  Issue: 2 )