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Reducing the communication bottleneck via on-chip cosimulation of gate-level HDL and C-models on a hardware accelerator

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5 Author(s)
Maili, A. ; Inst. for Tech. Informatics, Graz Univ. of Technol., Austria ; Steger, C. ; Weib, R. ; Quigley, R.
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This paper presents a hardware acceleration system based on a gate-level accelerator and an on-chip microprocessor enabling co-simulation of C-models with gate-level modules on the accelerator. This solution tackles the communication bottleneck that occurs when using hardware accelerators or emulators to speed up simulation. We analyze this bottleneck for the APPLES gate-level hardware accelerator and present the speedup that can be achieved by a prototype of the PowerPC-APPLES accelerator implemented on a Virtex2Pro FPGA on a PCI card.

Published in:

VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on

Date of Conference:

11-12 May 2005