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Configurable multiprocessors for high-performance MPEG-4 video coding

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1 Author(s)
Chouliaras, V.A. ; Loughborough Univ., UK

We investigate the performance improvement of a multithreaded MPEG-4 video encoder executing on a configurable, extensible, SoC multiprocessor. Architecture-level results indicate a significant reduction in the dynamic instruction count of the order of 83% for 16 processor contexts compared to the original single-thread implementation. We extended an open-source 32-bit RISC CPU to include hardware-based multi-processing primitives and associated support state and implemented a parametric, bus-based SoC multiprocessor as the target platform for the threaded video encoder.

Published in:

VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on

Date of Conference:

11-12 May 2005