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Among many recently proposed on-chip jitter measurement designs, Vernier delay line (VDL) is one of the most widely adopted methods that can achieve fine resolution. However, there are two major design challenges: the first is the mismatching of delay buffers; the second is the unavailability of an on-chip jitter free reference signal. To overcome these two challenges, we propose a self-refereed on-chip jitter measurement circuit. This measurement circuit eliminates the requirement to a jitter free reference signal. In addition, it utilizes Vernier oscillators to alleviate the mismatching effect in Vernier lines. Using this design, the jitter distribution and jitter RMS value can be characterized. To validate the design, the circuit has been implemented using IBM 7 HP 0.18um CMOS technology.
Date of Conference: 11-12 May 2005