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Design and implementaion of a 2D-DCT architecture using coefficient distributed arithmetic [implementaion read implementation]

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3 Author(s)
Ghosh, S. ; Center for Adv. Comput. Studies, Louisiana Univ., Lafayette, LA, USA ; Venigalla, S. ; Bayoumi, M.

The paper describes the design and implementation of an 8 ×8 2D DCT chip for use in low-power applications. The design exploits a coefficient distributed arithmetic (CoDA) scheme as opposed to the prevalent data distributed arithmetic (DDA) schemes to achieve low power consumption. The architecture uses no ROMs and uses minimum number of additions by exploiting the redundancy in the adder arrays. The described architecture for the CoDA scheme is implemented on FPGA and has been fabricated on silicon. The fabricated chip computes 8 ×8 2D DCT @ 50 MHz consuming around 137mW of power.

Published in:

VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on

Date of Conference:

11-12 May 2005