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Exploiting an infrastructure IP to reduce memory diagnosis costs in SoCs

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4 Author(s)
P. Bernardi ; Dipt. di Automatica e Informatica, Politecnico di Torino, Italy ; M. Grosso ; M. Rebaudengo ; M. Sonza Reorda

Discriminating between good and faulty chips is often not enough during IC manufacturing phases, where a complete understanding about failure mechanisms is required to ramp up production yield. When considering embedded memories, information about the whole set of faults needs to be extracted from the IC and processed: this asks for solutions supporting high data volume transfer. We propose an embedded architecture allowing efficient diagnosis of SoCs containing several BISTed memory cores, which minimizes ATE memory requirements for pattern storage and drastically speeds up the complete diagnostic procedure. Experimental results highlight the convenience of the approach with respect to alternative ATE driven procedures, while resorting to negligible area overhead.

Published in:

European Test Symposium (ETS'05)

Date of Conference:

22-25 May 2005