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Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation

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3 Author(s)
Iwagaki, T. ; Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan ; Ohtake, S. ; Fujiwara, H.

This paper presents a transition test generation method for acyclic sequential circuits. In this method, to generate test sequences for transition faults in a given acyclic sequential circuit, constrained combinational stuck-at test generation is performed on its double time-expansion model that is composed of two copies of a time-expansion model of the given circuit. This method is complete, i.e., this method can generate test sequences for all the testable transition faults and can identify all the untestable transition faults in a given acyclic sequential circuit. Experimental results show that our method can achieve higher fault efficiency with drastically shorter test generation time than that achieved by a conventional method.

Published in:

Test Symposium, 2005. European

Date of Conference:

22-25 May 2005