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Design of experiments on an EMC test chip for the interrogation of SI and EMC measures

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2 Author(s)
M. Coenen ; Philips Semicond., Eindhoven, Netherlands ; R. Derikx

Many IC design houses, manufacturers and silicon foundries give SI and EMC rules and guidelines but the possible interaction between the various measures is mostly unknown. An EMC test-chip has been developed with the aim to evaluate the presently known EMC design rules and to investigate some new measures like power grid adjustments and dampening resistances between peripheral supply and substrate. Instead of carrying out an experiment permuting one factor at a time (OFAT) a multi-parameter analysis technique, using design-of-experiments (DOE) was created with ultimately positive results. The experiment has been carried out with 8 core and 5 peripheral parameter settings considering 7 responses: means 7(38+35)=47628 relations. This first EMC test-chip has been designed in C075 (CMOS035) technology, as with the start of this project the proper RF device modelling was available. The evaluation results of the EMC test-chip are included in the on-chip EMC design rules for C075 and newer process technologies.

Published in:

Electromagnetic Compatibility, 2003. EMC '03. 2003 IEEE International Symposium on  (Volume:2 )

Date of Conference:

11-16 May 2003