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A continuous-time ΣΔ Modulator with reduced sensitivity to clock jitter through SCR feedback

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3 Author(s)
Ortmanns, M. ; sci-worx GmbH, Hannover, Germany ; Gerfers, F. ; Manoli, Y.

This paper presents a means to overcome the high sensitivity of continuous-time sigma-delta (ΣΔ) modulators to clock jitter by using a modified switched-capacitor structure with resistive element in the continuous-time feedback digital-analog converter (DAC). The reduced sensitivity to jitter is both simulated and proven by measured results from two implemented third-order modulators. Additionally, the nonideal behavior is analyzed analytically and by simulations.

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Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:52 ,  Issue: 5 )