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An analog floating-gate node for Supervised learning

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2 Author(s)
Hasler, P. ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA ; Dugger, J.

We present an improved analog floating-gate pFET synapse that implements a supervised learning algorithm similar to the least mean square (LMS) learning rule. Weight decay plays a key role in several learning rules; this floating-gate synapse exhibits this behavior. We examine implications of the weight decay appearing in the correlation learning rule realized in the floating-gate synapse and provide experimental data characterizing the synapse and its performance in one-input and two-input LMS networks. Analog floating-gate synapses will enable larger-scale, on-chip learning networks than previously possible.

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Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:52 ,  Issue: 5 )