Skip to Main Content
This paper presents a new approach to compact thermal modeling. The paper shows how a parameterized reduced thermal model of an IC component can be created based on a parametric model reduction technique. By applying this technique, a large system of equations characterizing a discretized fully detailed numerical thermal model can be drastically reduced. The final product of a parameterized model reduction procedure is a set of small matrices presenting an abstract description of the component thermal behavior. The reduced system can be used to either synthesize a resistive network or formulate a set of connection equations to be connected to higher simulation levels. External boundary conditions are parameters of the reduced model and can be specified at simulation time. A parameterized reduced thermal model is found to have a number of advantages over an optimized resistor network model. The model can be generated quickly (one lower-upper (LU) decomposition is needed), high accuracies are obtained with a typical error of less than 0.1%. The technique also predicts temperature at all internal nodes of the original detailed model not just a single junction temperature. In this paper, the new technique is demonstrated through two examples of realistic IC components: a GaAs power amplifier and a generic multichip module ball grid array package. Both reduced models are connected to substrates in a number of different configurations. Thermal analysis performed in each case shows the importance of the geometric configuration of the connections on predictive capability.