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On-chip test circuitry for a 2-ns cycle, 512-kb CMOS ECL SRAM

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4 Author(s)
Schuster, S.E. ; IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA ; Chappell, T.I. ; Chappell, B.A. ; Franch, R.L.

On-chip test circuitry that provides 8-b-deep emitter-coupled logic (ECL) level patterns to 12 input pads of a 512-kb CMOS ECL static RAM (SRAM) at cycle times as fast as 1.4 ns has been built in a 0.8- mu m CMOS technology with Leff=0.5 mu m. A unique approach for synchronizing the input signals to the chip-select signal in order to provide an optimum setup time and data-valid windows as the operating frequency changes is described. Measured results and extensive simulation demonstrate the stability of the on-chip test circuitry for cycle times of 1.4-50 ns. The on-chip test circuitry makes it possible to test the SRAM chip at its pipelined cycle time. In addition, the speed of the on-chip test circuitry will track future technology improvements, making it possible to generate test patterns as SRAM performance continues to improve.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:27 ,  Issue: 7 )

Date of Publication:

Jul 1992

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