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A submicrometer NMOS multiplexer-demultiplexer chip set for 622.08-Mb/s SONET applications

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7 Author(s)
Weston, H.T. ; AT&T Bell Lab., Murray Hill, NJ, USA ; Banu, M. ; Fang, S.-C. ; Diodato, P.W.
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The development of a low-power 12-channel multiplexer-demultiplexer pair that is clocked at the standard synchronous optical network (SONET) rate of 622.08 MHz is discussed. Each device has been integrated in silicon using a 0.75- mu m NMOS VLSI technology that provides high fabrication yield at relatively low cost. Highlighted are the analog interface circuits of the two chips. These include a phase splitter and amplifier for the maser clock input, a precision 50- Omega output driver for high-speed synchronous-transport-signal-12 (STS-12) data, as well as input amplifier and an output stage for low-speed differential STS-1 data.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:27 ,  Issue: 7 )

Date of Publication:

Jul 1992

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