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A unified theory for mixed CMOS/BiCMOS buffer optimization

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1 Author(s)
Sakurai, T. ; Toshiba Corp., Kawasaki, Japan

A simple yet realistic gate sizing theory is presented to optimize delay of a cascaded gate buffer. The theory is based on the fact that CMOS/BiCMOS gate delay is linearly dependent on fan-out f, that is the delay can be expressed as Af+B, where A and B are coefficients. The optimum fan-out fOPT is shown to be approximated as e+B/1.5A for a gate chain. The theory covers various BiCMOS/CMOS gate types such as NANDs and NORs in a unified framework. The existence of spurious capacitance is shown to increase the size of all transistors compared with the case without the spurious capacitance.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:27 ,  Issue: 7 )

Date of Publication:

Jul 1992

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