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Optimization of buffer stages in bipolar VLSI systems

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2 Author(s)
Konstadinidis, G.K. ; Inst. of Microelectron., Tech. Univ. of Berlin, Germany ; Berger, Horst H.

Discusses the power-delay optimization of emitter followers, of level shifters used in cascode emitter coupled logic (CECL) VLSI systems, and of Darlington buffers. Quasi-linear large-signal circuit models are developed. From these, analytical delay expressions for all these buffer stages in high-speed operation, where the driving capability is substantially reduced, are extracted. In addition, the critical bias current for minimum power-delay product is determined. Basically, the same delay expressions apply also to BiCMOS buffers. The simplicity of these expressions allows a fast optimization procedure, with little loss of accuracy, as the calculation results deviate from simulation mostly less than 5%.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:27 ,  Issue: 7 )