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The design of high-speed current mode logic latches is discussed, using analytical expressions for delay. An open circuit time constant method is utilized throughout this paper, though similar results were obtained from a charge control analysis. Emphasis is placed on the variables that are under the control of the circuit designer, as opposed to the device designer. Circuit delay is calculated with respect to device area, current density, amplitude, and a keep-alive current. In particular, the keep-alive current gives the circuit designer control over the average transconductance of switching transistors, independent of their bias currents. The cost of the keep-alive current is the loss of output amplitude. The effects of transmission lines and peaking inductors are discussed in a qualitative manner. Latch designs were tested with static divide-by-two frequency dividers. Results of several dividers (both SiGe and InP) are shown and compared with the theory.