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A dual-loop delay-locked loop (DLL) was implemented by using an analog voltage-controlled delay line (VCDL) for low jitter. An infinite phase-shift capability with seamless phase change was achieved by adding a look-ahead VCDL. A low jitter was achieved for the entire input frequency lock range from 60 to 760 MHz by using the adaptive bandwidth scheme in both reference and fine loops. A wide input-frequency lock range was achieved due to the combined effects of the dual-loop architecture and the extra phase detector of the reference DLL. The extra phase detector eliminated the constraint on the initial VCDL delay for DLL to be locked. Measurements on the fabricated chip by using a 0.18-μm CMOS process showed a power consumption of 63 mW at 700 MHz, an active chip area of 370×510 μm2, and peak-to-peak jitters of 28 and 39 ps at the 700-MHz synchronous and plesiochronous operations, respectively.