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A 150-MS/s 8-b 71-mW CMOS time-interleaved ADC

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4 Author(s)
S. Limotyrakis ; Center for Integrated Syst., Stanford, CA, USA ; S. D. Kulchycki ; D. K. Su ; B. A. Wooley

A pipelined analog-to-digital converter (ADC) architecture suitable for high-speed (150 MHz), Nyquist-rate A/D conversion is presented. At the input of the converter, two parallel track-and-hold circuits are used to separately drive the sub-ADC of a 2.8-b first pipeline stage and the input to two time-interleaved residue generation paths. Beyond the first pipeline stage, each residue path includes a cascade of two 1.5-b pipeline stages followed by a 4-b "backend" folding ADC. The full-scale residue range at the output of the pipeline stages is half that of the converter input range in order to conserve power in the operational amplifiers used in each residue path. An experimental prototype of the proposed ADC has been integrated in a 0.18-μm CMOS technology and operates from a 1.8-V supply. At a sampling rate of 150 MSample/s, it achieves a peak SNDR of 45.4 dB for an input frequency of 80 MHz. The power dissipation is 71 mW.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:40 ,  Issue: 5 )