Skip to Main Content
To meet varying requirements for a wide variety of contemporary media applications with evolving standards, a generic and flexible media-processing design platform is essential to manage increasing system-on-a-chip (SoC) design complexity with minimal design cost and time-to-market. A possible solution to the problem is combining several reconfigurable hardware resources with a programmable processor into a single-chip device such that flexibility and performance can be pursued at the same time. While several innovative reconfigurable architectures have been reported in the literature, none of these architectures are poised to provide the ease of software development for sophisticated SoC-based media processing applications. In this paper, we propose a new flexible heterogeneous multicore architecture system, which comprises a main reduced-instruction set computer (RISC) processor and a reconfigurable controller along with other configurable hardware blocks such as DSP processors or intellectual property blocks (IPBs). The key idea is that the interactions of those hardware blocks are grouped together and instructions are defined to express a middle-grained parallelism among intellectual property blocks in terms of several sequences of customized long instruction words (CLIW). A CLIW ROM is reconfigurable in response to application changes. We design the instruction set architecture, called reconfigurable controller, and show the implementation details. In addition, we demonstrate the necessary software tools that are needed to generate the suitable CLIW instruction code for applications.
Circuits and Systems for Video Technology, IEEE Transactions on (Volume:15 , Issue: 5 )
Date of Publication: May 2005