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A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR

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4 Author(s)
Jipeng Li ; Design Center, Nat. Semicond. Inc., Salem, NH, USA ; Gil-Cho Ahn ; Dong-Young Chang ; Un-Ku Moon

An ultra-low-voltage CMOS two-stage algorithm ADC featuring high SFDR and efficient background calibration is presented. The adopted low-voltage circuit technique achieves high-accuracy high-speed clocking without the use of clock boosting or bootstrapping. A resistor-based input sampling branch demonstrates high linearity and inherent low-voltage operation. The proposed background calibration accounts for capacitor mismatches and finite opamp gain error in the MDAC stages via a novel digital correlation scheme involving a two-channel ADC architecture. The prototype ADC, fabricated in a 0.18 μm CMOS process, achieves 77-dB SFDR at 0.9 V and 5MSPS (30 MHz clocking) after calibration. The measured SNR, SNDR, DNL, and INL at 80 kHz input are 50 dB, 50 dB, 0.6 LSB, and 1.4 LSB, respectively. The total power consumption is 12 mW, and the active die area is 1.4 mm2.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:40 ,  Issue: 4 )