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A third-order ΣΔ modulator in 0.18-μm CMOS with calibrated mixed-mode integrators

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3 Author(s)
Jae Hoon Shim ; Electron. & Telecommun. Res. Inst., Daejeon, South Korea ; In-Cheol Park ; Beomsup Kim

This paper describes a third-order sigma-delta (ΣΔ) modulator that is designed and implemented in 0.18-μm CMOS process. In order to increase the dynamic range, this modulator takes advantage of mixed-mode integrators that consist of analog and digital integrators. A calibration technique is applied to the digital integrator to mitigate mismatch between analog and digital paths. It is shown that the presented modulator architecture can achieve a 12-dB better dynamic range than conventional structures with the same oversampling ratio (OSR). The experimental prototype chip achieves a 76-dB dynamic range for a 200-kHz signal bandwidth and a 55-dB dynamic range for a 5-MHz signal bandwidth. It dissipates 4 mW from 1.8-V supply voltages and occupies 0.7-mm2 silicon area.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:40 ,  Issue: 4 )