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SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction

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9 Author(s)

A 70-Mb SRAM is designed and fabricated on a 65-nm CMOS technology. It features a 0.57-μm2 6T SRAM cell with large noise margin down to 0.7 V for low-voltage operation. The fully synchronized subarray contains an integrated leakage reduction scheme with dynamically controlled sleep transistor. SRAM virtual ground in standby is controlled by programmable bias transistors to achieve good voltage control with fine granularity under process skew. It also has a built-in programmable defect "screen" circuit for high volume manufacturing. The measurements showed that the SRAM leakage can be reduced by 3-5× while maintaining the integrity of stored data.

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Solid-State Circuits, IEEE Journal of  (Volume:40 ,  Issue: 4 )