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We propose a new CAM architecture for the large-scale integration and low-power operation of a network router application. This CAM reduces entry count by an average of 52%, using a newly developed one-hot-spot block code. This code eliminates redundancy in a memory cell and improves the efficiency of IP address compression. To implement the proposed code, a hierarchical match-line structure and an on-chip entry compression/extraction scheme are introduced. With this architecture, a search-depth control scheme deactivates unnecessary search lines and reduces power consumption by 45%. Using a DRAM cell, our new content addressable memory (CAM) can achieve 1.5 million entries in 0.13-μm technology, which is six times more than a conventional static ternary CAM.
Date of Publication: April 2005