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Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect

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4 Author(s)
N. Miura ; Dept. of Electron. & Electr. Eng., Keio Univ., Yokohama, Japan ; D. Mizoguchi ; T. Sakurai ; T. Kuroda

A wireless bus for stacked chips was developed by utilizing inductive coupling among them. This paper discusses inductor layout optimization and transceiver circuit design. The inductive coupling is analyzed by a simple equivalent circuit model, parameters of which are extracted by a magnetic field model based on the Biot-Savart law. Given communication distance, transmit power, data rate, and SNR budget, inductor layout size is minimized. Two receiver circuits, signal sensitive and yet noise immune, are designed for inductive nonreturn-to-zero (NRZ) signaling where no signal is transmitted when data remains the same. A test chip was fabricated in 0.35-μm CMOS technology. Accuracy of the models is verified. Bit-error rate is investigated for various inductor layouts and communication distance. The maximum data rate is 1.25 Gb/s/channel. Power dissipation is 43 mW in the transmitter and 2.6 mW in the receiver at 3.3 V. If chip thickness is reduced to 30 μm in 90-nm device generation, power dissipation will be 1 mW/channel or bandwidth will be 1 Tb/s/mm2.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:40 ,  Issue: 4 )